Silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) technology has recently received a great degree of attention because it potentially offers high circuit speeds through reduction in parasitic capacitance, freedom from latch-up, higher density, and resistance to transient radiation effects. Until very recently, most SOI work has involved relatively thick (300 to 500 nm) silicon layers. Heretofore, CMOS circuits made on such layers have been found to suffer from floating body effects and short channel characteristics. These deficiencies are the main barrier to building high density, high speed SOI circuits using submicron MOS devices.
In an effort to avoid these problems inherent in such relatively thick films, researchers have turned to ultra-thin (less than 100 nm) Si films made on buried oxide insulators, i.e., SOI structures. Theoretical modeling and initial experimental work has demonstrated the advantages of fabricating CMOS devices in ultra-thin SOI films. These devices are an attractive choice for building the next generation ultra-large scale integrated (ULSI) circuits. (See "Comparison of Thin Film Transistor and SOI Technologies", H. W. Lam and M. J. Thompson (Eds), North Holland Publishing Company, New York, 1984 and M. Yoshimi, T. Wada, K. Kato, H. Tango, Technical Digest of the 1987 International Electron Devices Meeting, IEEE, Piscataway, N.J. 1987, p. 640.)
However, fabrication of CMOS devices in ultra-thin silicon films is not free from problems of its own. In addition to the difficulties associated with obtaining near defect-free SOI substrates, the next most difficult problem is the making of suitable contacts to the device in the ultra-thin source and drain regions.
When the Si film is extra-thin, the thick metallization contact film necessary for low resistance connection to the transistor source and drain regions has a tendency to dissolve the ultra-thin silicon film to which it is supposed to make contact.
If the full thickness of the ultra-thin silicon film dissolves, the contact fails. Many solutions to the problem of making contact to very shallow source and drain regions have been proposed in the prior art (W. R. Lynch, Technical Digest of the 1987 International Electron Devices Meeting, IEEE, Piscataway, N.J. 1987, p. 354). All the practical solutions involve the use of novel materials, structures, and processes resulting in fabrication complexity, increased costs and reduced yields. Moreover, all the methods used for contacts to ultra-thin source and drain regions become even more difficult to implement in the specific example of SOI substrates with a silicon thickness of less than 100 nm.